Read-out calibration of a SOI capacitive transducer using the pull-in voltage

The pull-in voltage of a parallel plate electrostatic transducer is used to determine the amount of over-etching in fabricated devices. A detailed analysis of the capacitor behaviour over the full displacement range yields a model, which is used to describe the relation between over-etching and measured pull-in voltage. SEM photos confirm the over-etching measurement based on pull-in voltage. This information is used to linearize a charge amplifying read-out circuit with an intrinsic nonlinear transfer function. The remaining nonlinearity error of the read-out is less than 1%. (Some figures in this article are in colour only in the electronic version)